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general description the ds24b33 is a 4096-bit, 1-wire ? eeprom orga- nized as 16 memory pages of 256 bits each. data is written to a 32-byte scratchpad, verified, and then copied to the eeprom memory. the ds24b33 commu- nicates over a single-conductor 1-wire bus. the com- munication follows the standard 1-wire protocol. each device has its own unalterable and unique 64-bit regis- tration number that is factory programmed into the chip. the registration number is used to address the device in a multidrop 1-wire net environment. the eeprom provides 200,000 cycles of write/erase endurance at +25?. the ds24b33 is software compatible to the ds2433. applications storage of calibration constants board identification storage of product revision status features ? 4096 bits of nonvolatile eeprom partitioned into sixteen 256-bit pages ? read and write access is highly backward- compatible to the ds2433 ? 256-bit scratchpad with strict read/write protocols ensures integrity of data transfer ? 200,000 write/erase cycle endurance at +25? ? unique, factory-programmed, 64-bit registration number ensures error-free device selection and absolute part identity ? switchpoint hysteresis to optimize performance in the presence of noise ? communicates to host at 15.4kbps or 125kbps using 1-wire protocol ? low-cost through-hole and smd packages ? operating range: +2.8v to +5.25v, -40? to +85? ? iec 1000-4-2 level 4 esd protection (?kv contact, ?5kv air, typical) for io pin ds24b33 4kb 1-wire eeprom with 200k write/erase cycles ________________________________________________________________ maxim integrated products 1 ordering information io r pup v cc c gnd ds24b33 typical operating circuit 19-5759; rev 0; 2/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. part temp range pin-package ds24b33+ -40 c to +85 c to-92 ds24b33+t&r -40 c to +85 c to-92 ds24b33s+ -40 c to +85 c 8 so (208 mils) ds24b33s+t&r -40 c to +85 c 8 so (208 mils) 1-wire is a registered trademark of maxim integrated products, inc.
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (t a = -40? to +85?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. io voltage range to gnd ........................................-0.5v to +6v io sink current....................................................................20ma operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-55? to +125? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) to-92 ...........................................................................+250? so ................................................................................+260? parameter symbol conditions min typ max units io pin: general data 1-wire pullup voltage v pup (notes 2, 3) 2.8 5.25 v 1-wire pullup resistance r pup (notes 2, 4) 0.3 2.2 k input capacitance c io (notes 5, 6) 2000 pf input load current i l io at v pupmax 0.05 5 a high-to-low switching threshold v tl (notes 6, 7, 8) 0.5 v pup - 1.8 v input low voltage v il (notes 2, 9) 0.5 v low-to-high switching threshold v th (notes 6, 7, 10) 1.0 v pup - 1.0 v switching hysteresis v hy (notes 6, 7, 11) 0.2 1.7 v output low voltage v ol at 4ma (note 12) 0.4 v standard speed 5 overdrive speed 2 v pup +4.5v 1 directly prior to reset pulse 640 s 5 recovery time (notes 2, 13) t rec directly prior to reset pulse > 640s 10 s standard speed 65 standard speed, v pup +4.5v 61 overdrive speed 8 time-slot duration (notes 2, 14) t slot overdrive speed, v pup +4.5v 7 s io pin: 1-wire reset, presence-detect cycle standard speed, t rec before reset = 10s 480 960 standard speed, t rec before reset = 5s 480 640 reset low time (note 2) t rstl overdrive speed 48 80 s standard speed 15 60 presence-detect high time t pdh overdrive speed 2 6 s standard speed 60 240 presence-detect low time t pdl overdrive speed 8 24 s standard speed 60 75 presence-detect sample time (notes 2, 15) t msp overdrive speed 6 10 s
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles _______________________________________________________________________________________ 3 electrical characteristics (continued) (t a = -40? to +85?.) (note 1) parameter symbol conditions min typ max units io pin: 1-wire write standard speed 60 120 write-zero low time (notes 2, 16) t w0l overdrive speed 6 16 s standard speed 5 15 write-one low time (notes 2, 16) t w1l overdrive speed 1 2 s io pin: 1-wire read standard speed 5 15 - read low time (notes 2, 17) t rl overdrive speed 1 2 - s standard speed t rl + 15 read sample time (notes 2, 17) t msr overdrive speed t rl + 2 s eeprom programming current i prog (note 18) 2 ma programming time t prog (note 19) 5 ms at +25c 200,000 write/erase cycles (endurance) (notes 20, 21) n cy at +85c (worst case) 50,000 data retention (notes 22, 23, 24) t dr at +85c (worst case) 40 years note 1: not all parameters are tested at all temperatures. note 2: system requirement. note 3: when operating near the minimum operating voltage (2.8v), a falling edge slew rate of 15v/? or faster is recommended. note 4: maximum allowable pullup resistance is a function of the number of 1-wire devices in the system, 1-wire recovery times, and current requirements during eeprom programming. the specified value here applies to systems with only one device and with the minimum 1-wire recovery times. for more heavily loaded systems, an active pullup such as that found in the ds2482-x00 or ds2480b may be required. note 5: capacitance on the data pin could be 2500pf when v pup is first applied. if a 2.2k resistor is used to pull up the data line, then 15? after v pup has been applied, the parasite capacitance does not affect normal communications. note 6: guaranteed by design, characterization, and/or simulation only. not production tested. note 7: v tl , v th , and v hy are a function of the internal supply voltage, which is a function of v pup , r pup , 1-wire timing, and capacitive loading on io. lower v pup , higher r pup , shorter t rec , and heavier capacitive loading all lead to lower values of v tl , v th , and v hy . note 8: voltage below which, during a falling edge on io, a logic 0 is detected. note 9: the voltage on io must be less than or equal to v ilmax at all times while the master is driving io to a logic 0 level. note 10: voltage above which, during a rising edge on io, a logic 1 is detected. note 11: after v th is crossed during a rising edge on io, the voltage on io must drop by at least v hy to be detected as logic 0. note 12: the i-v characteristic is linear for voltages less than +1v. note 13: applies to a single ds24b33 attached to a 1-wire line. note 14: defines maximum possible bit rate. equal to 1/(t w0lmin + t recmin ). note 15: interval after t rstl during which a bus master is guaranteed to sample a logic 0 on io if there is a ds24b33 present. minimum limit is t pdhmax ; maximum limit is t pdhmin + t pdlmin . note 16: in figure 11 represents the time required for the pullup circuitry to pull the voltage on io up from v il to v th . the actual maximum duration for the master to pull the line low is t w1lmax + t f - and t w0lmax + t f - , respectively. note 17: in figure 11 represents the time required for the pullup circuitry to pull the voltage on io up from v il to the input high threshold of the bus master. the actual maximum duration for the master to pull the line low is t rlmax + t f . note 18: current drawn from io during the eeprom programming interval. the pullup circuit on io should be such that during the programming interval, the voltage at io is greater than or equal to v pupmin . if v pup in the system is close to v pupmin , then a low-impedance bypass of r pup , which can be activated during programming, may need to be added. note 19: the t prog interval begins after the trailing rising edge on io for the last time slot of the e/s byte for a valid copy scratch- pad sequence. the interval ends once the device? self-timed eeprom programming cycle is complete and the current drawn by the device has returned from i prog to i l .
1 2 3 4 n.c. n.c. io gnd n.c. n.c. n.c. n.c. 8 7 6 5 ds24b33 so (208 mils) top view + electrical characteristics (continued) (t a = -40? to +85?.) (note 1) note 20: write-cycle endurance is degraded as t a increases. note 21: not 100% production tested; guaranteed by reliability monitor sampling. note 22: data retention is degraded as t a increases. note 23: guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet limit at operating temperature range is established by reliability testing. note 24: eeprom writes can become nonfunctional after the data-retention time is exceeded. long-time storage at elevated tem- peratures is not recommended; the device can lose its write capability after 10 years at +125? or 40 years at +85?. ds24b33 4kb 1-wire eeprom with 200k write/erase cycles 4 _______________________________________________________________________________________ 2 3 1 2 3 1 3 2 1 n.c. io gnd to-92 front view (t&r version) front view side view pin configurations
ds24b33 detailed description the ds24b33 combines 4kb of data eeprom with a fully featured 1-wire interface in a single chip. the memory is organized as 16 pages of 256 bits each. a volatile 256-bit memory page called the scratchpad acts as a buffer when writing data to the eeprom to ensure data integrity. data is first written to the scratch- pad, from which it can be read back for verification before transferring it to the eeprom. the operation of the ds24b33 is controlled over the single-conductor 1-wire bus. device communication follows the standard 1-wire protocol. the energy required to read and write the ds24b33 is derived entirely from the 1-wire com- munication line. each ds24b33 has its own unalterable and unique 64-bit registration number. the registration number guarantees unique identification and is used to address the device in a multidrop 1-wire net environ- ment. multiple ds24b33 devices can reside on a com- mon 1-wire bus and be operated independently of each other. applications of the ds24b33 include cali- bration data storage, pcb identification, and storage of product revision status. the ds24b33 provides a high degree of backward compatibility with the ds2433, including having the same family code. overview figure 1 shows the relationships between the major control and memory sections of the ds24b33. the ds24b33 has four main data components: 64-bit pin description to-92 so name function 1 4 gnd ground reference 2 3 io 1-wire bus interface. open-drain pin that requires external pullup resistor. 3 1, 2, 5C8 n.c. not connected 4kb 1-wire eeprom with 200k write/erase cycles _______________________________________________________________________________________ 5 ds24b33 1-wire function control 1-wire net parasite power crc-16 generator 64-bit registration number 32-byte scratchpad data memory 16 pages of 32 bytes each memory function control unit figure 1. block diagram
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles 6 _______________________________________________________________________________________ available commands: data field affected: read rom match rom search rom skip rom resume overdrive-skip rom overdrive-match rom 64-bit reg. #, rc-flag 64-bit reg. #, rc-flag 64-bit reg. #, rc-flag rc-flag rc-flag rc-flag, od-flag 64-bit reg. #, rc-flag, od-flag 1-wire rom function commands write scratchpad read scratchpad copy scratchpad read memory 32-byte scratchpad, flags 32-byte scratchpad data memory data memory ds24b33-specific memory function commands command level: ds24b33 figure 2. hierarchical structure for 1-wire protocol msb 8-bit crc code 48-bit serial number msb msb lsb lsb lsb 8-bit family code (23h) msb lsb figure 3. 64-bit registration number registration number, 32-byte scratchpad, sixteen 32-byte pages of eeprom, and a crc-16 generator. figure 2 shows the hierarchical structure of the 1-wire protocol. the bus master must first provide one of the seven rom (network) function commands: read rom, match rom, search rom, skip rom, resume, overdrive-skip rom, or overdrive-match rom. upon completion of an overdrive rom com- mand byte executed at standard speed, the device enters overdrive mode where all subsequent commu- nication occurs at a higher speed. figure 9 describes the protocol required for these rom func- tion commands. after a rom function command is successfully executed, the memory functions become accessible and the master can provide any one of the four memory function commands. figure 7 describes the protocol for these commands. all data is read and written least significant bit (lsb) first. parasite power figure 1 shows the parasite power supply. this circuitry ?teals?power whenever the io input is high. io pro- vides sufficient power as long as the specified timing and voltage requirements are met. 64-bit registration number each ds24b33 contains a unique registration number that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a cyclic redundancy check (crc) of the first 56 bits. see figure 3 for details. the 1-wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the 1-wire crc is available in application note 27: understanding and using cyclic redundancy checks with maxim i button ? products . i button is a registered trademark of maxim integrated products, inc.
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles _______________________________________________________________________________________ 7 1st stage 2nd stage 3rd stage 4th stage 7th stage 8th stage 6th stage 5th stage x 0 x 1 x 2 x 3 x 4 polynomial = x 8 + x 5 + x 4 + 1 input data x 5 x 6 x 7 x 8 figure 4. 1-wire crc generator 32-byte intermediate storage scratchpad address 0000h to 001fh 32-byte final storage eeprom page 0 0020h to 003fh 32-byte final storage eeprom page 1 0040h to 01dfh final storage eeprom pages 2 to 14 01e0h to 01ffh 32-byte final storage epprom page 15 figure 5. memory map the shift register bits are initialized to 0. then, starting with the lsb of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, the serial number is entered. after the last bit of the serial number has been entered, the shift register contains the crc value. shifting in the 8 bits of the crc returns the shift register to all 0s. memory the ds24b33 eeprom array (figure 5) consists of 16 pages of 32 bytes each, starting at address 0000h and ending at address 01ffh. in addition to the eeprom, the device has a 32-byte volatile scratchpad. writes to the eeprom array are a two-step process. first, data is written to the scratchpad and then copied into the main array. the user can verify the data in the scratch- pad prior to copying.
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles 8 _______________________________________________________________________________________ memory access address registers and transfer status the ds24b33 employs three address registers: ta1, ta2, and e/s (figure 6). registers ta1 and ta2 must be loaded with the target address to which the data is written or from which data is read. register e/s is a read-only transfer status register used to verify data integrity with write commands. es bits e[4:0] are loaded with the incoming t[4:0] on a write scratchpad command and increment on each subsequent data byte. this is, in effect, a byte-ending offset counter within the 32-byte scratchpad. bit 5 of the e/s register, called the partial byte flag (pf), is set if the number of data bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not valid due to a loss of power. a valid write to the scratchpad clears the pf bit. bit 6 has no function; it always reads 0. the highest valued bit of the e/s register, called authoriza- tion accepted (aa), is valid only if the pf flag reads 0. if pf is 0 and aa is 1, the data stored in the scratchpad has already been copied to the target memory address. writing data to the scratchpad clears this flag. writing with verification to write data to the ds24b33, the scratchpad must be used as intermediate storage. first, the master issues the write scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. under certain conditions (see the write scratchpad [0fh] section) the master receives an inverted crc-16 of the command, address, and data at the end of the write scratchpad command sequence. knowing this crc value, the master can compare it to the value it has calculated itself to decide if the commu- nication was successful and proceed to the copy scratchpad command. if the master could not receive the crc-16, it should send the read scratchpad com- mand to verify data integrity. as a preamble to the scratchpad data, the ds24b33 repeats the target address ta1 and ta2 and sends the contents of the e/s register. if the pf flag is set, data did not arrive cor- rectly in the scratchpad or there was a loss of power since data was last written to the scratchpad. the mas- ter does not need to continue reading; it can start a new trial to write data to the scratchpad. similarly, a set aa flag together with a cleared pf flag indicates that the device did not recognize the write command. if everything went correctly, both flags are cleared and the ending offset indicates the address of the last byte written to the scratchpad. now the master can continue reading and verifying every data byte. after the master has verified the data, it can send the copy scratchpad command, for example. this command must be fol- lowed exactly by the data of the three address registers ta1, ta2, and e/s. the master should obtain the con- tents of these registers by reading the scratchpad. as soon as the ds24b33 has received these bytes correctly, it starts copying the scratchpad data to the requested location. bit number 7 6 5 4 3 2 1 0 target address (ta1) t7 t6 t5 t4 t3 t2 t1 t0 target address (ta2) t15 t14 t13 t12 t11 t10 t9 t8 ending address with data status (e/s) (read only) aa 0 pf e4 e3 e2 e1 e0 figure 6. address registers
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles _______________________________________________________________________________________ 9 memory function commands the memory function flowchart (figure 7) describes the protocols necessary for accessing the memory of the ds24b33. the target address registers ta1 and ta2 are used for both read and write. the communica- tion between the master and the ds24b33 takes place either at standard speed (default, od = 0) or at over- drive speed (od = 1). if not explicitly set into the over- drive mode, the ds24b33 assumes standard speed. write scratchpad [0fh] the write scratchpad command applies to the data memory. after issuing the write scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. the data is written to the scratchpad starting at the byte offset of t[4:0]. the es bits e[4:0] are loaded with the starting byte offset and increment with each subse- quent byte. effectively, e[4:0] is the byte offset of the last full byte written to the scratchpad. only full bytes are accepted. if the last byte is incomplete, its content is ignored and pf is set. when executing the write scratchpad command, the crc generator inside the ds24b33 (figure 13) calcu- lates a 16-bit crc of the entire data stream, starting at the command code and ending at the last data byte as sent by the master. this crc is generated using the crc-16 polynomial (x 16 + x 15 + x 2 + 1) by first clear- ing the crc generator and then shifting in the com- mand code (0fh) of the write scratchpad command, the target addresses ta1 and ta2 as supplied by the master, and all the data bytes. the master can end the write scratchpad command at any time. however, if the end of the scratchpad is reached (e[4:0] = 11111b), the master can send 16 read time slots to receive the crc generated by the ds24b33. the ds24b33? memory address range is 0000h to 01ffh. if the bus master sends a target address higher than this, the ds24b33? internal circuitry sets the 7 most significant address bits to zero as they are shifted into the internal address register. the read scratchpad command reveals the modified target address. the master identifies such address modifications by com- paring the target address read back to the target address transmitted. if the master does not read the scratchpad, a subsequent copy scratchpad command does not work because the most significant bits of the target address the master sends do not match the value that the ds24b33 expects. read scratchpad [aah] the read scratchpad command allows for verifying the target address and the integrity of the scratchpad data. after issuing the command code, the master begins reading. the first 2 bytes are the target address. the next byte is the ending offset/data status byte (e/s) fol- lowed by the scratchpad data beginning at the byte off- set (t[4:0]). the master should read through the end of the scratchpad. if the master continues reading beyond the end of the scratchpad, all data are logic 1s. copy scratchpad [55h] the copy scratchpad command is used to copy data from the scratchpad to the data memory. after issuing the copy scratchpad command, the master must pro- vide a 3-byte authorization pattern, which should have been obtained by an immediately preceding read scratchpad command. this 3-byte pattern must exactly match the data contained in the three address registers (ta1, ta2, e/s, in that order). if the pattern matches and the target address is valid, the aa flag is set and the copy begins. the data to be copied is determined by the three address registers. the scratchpad data from the beginning offset through the ending offset is copied to memory, starting at the target address. anywhere from 1 to 32 bytes can be copied with this command. the duration of the device? internal data transfer is t prog , during which the voltage on the 1-wire bus must not fall below v pupmin . a pattern of alternating 0s and 1s are transmitted after the data has been copied until the master issues a reset pulse. note: because of the memory architecture of the ds24b33, if a copy scratchpad command is interrupted during the write cycle, two consecutive copy scratchpad commands of the same data to the same location may be necessary to recover. to verify the suc- cess of the copy scratchpad command, always look for the alternating 0-to-1 pattern at the end of the copy scratchpad command flow and also read back the eep- rom page that was to be updated. if the alternating pattern appeared and the eeprom page data shows the intended new data, the write access was successful. no further action is required. in all other cases (alternat- ing 0-to-1 pattern is not seen or nonmatching eeprom page data), repeat the write scratchpad, copy scratchpad sequence until successful.
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles 10 ______________________________________________________________________________________ bus master tx memory function command ds24b33 clears pf, aa master tx data byte to scratchpad offset ds24b33 sets scratchpad offset = (t[4:0]) ds24b33 sets scratchpad offset = (t[4:0]) bus master rx "1"s ds24b33 increments scratchpad offset pf = 1 bus master tx eeprom array target address ta1 (t[7:0]), ta2 (t[15:8]) bus master rx ta1 (t[7:0]), ta2 (t[15:8]), and e/s byte 0fh write scratchpad? n y n y n y y n n master tx reset? partial byte? scratchpad offset = 11111b? master tx reset? ds24b33 sets (e[4:0]) = scratchpad offset ds24b33 tx crc-16 of command, address, and data bytes as they were sent by the bus master bus master rx "1"s y n master tx reset? y n master tx reset? y scratchpad offset = 11111b? y from rom functions flowchart (figure 9) to rom functions flowchart (figure 9) aah read scratchpad? n y n bus master rx data byte to scratchpad offset ds24b33 increments scratchpad offset to figure 7b from figure 7b figure 7a. memory function flowchart
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles ______________________________________________________________________________________ 11 ds24b33 tx "1" y n authorization code match? bus master rx ta1 (t[7:0]), ta2 (t[15:8]), and e/s byte bus master tx ta1 (t[7:0]), ta2 (t[15:8]) 55h copy scratchpad? n y f0h read memory? n y ds24b33 copies scratchpad data to address * *1-wire idle high for t prog for power. to figure 7a from figure 7a bus master rx "1"s master tx reset? n y master tx reset? master tx reset? n ds24b33 tx "0" y n n y aa = 1 bus master rx "1"s master tx reset? n y bus master rx "1"s ds24b33 sets memory address = (t[15:0]) bus master rx data byte from memory address y n n master tx reset? address < 1ffh? n y master tx reset? ds24b33 increments address counter y figure 7b. memory function flowchart (continued)
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles 12 ______________________________________________________________________________________ read memory [f0h] the read memory command is the general function to read from the ds24b33. after issuing the command, the master must provide a 2-byte target address, which should be in the range of 0000h to 01ffh. if the target address is higher than 01ffh, the ds24b33 changes the upper 7 address bits to 0. after the address is transmitted, the master reads data starting at the (modi- fied) target address and can continue until address 01ffh. if the master continues reading, the result is ffh. the read memory command can be ended at any point by issuing a reset pulse. note that the (modified) target address provided with the read memory com- mand overwrites the target address that was specified with a previously issued write scratchpad command. the read memory command overwrites the scratchpad with data from the target memory page. when reading the last byte of a memory page, the scratchpad is loaded with data from the next memory page. this could cause unexpected data to be loaded into the scratchpad. 1-wire bus system the 1-wire bus is a system that has a single bus master and one or more slaves. in all instances the ds24b33 is a slave device. the bus master is typically a microcon- troller. the discussion of this bus system is broken down into three topics: hardware configuration, trans- action sequence, and 1-wire signaling (signal types and timing). the 1-wire protocol defines bus transac- tions in terms of the bus state during specific time slots, which are initiated on the falling edge of sync pulses from the bus master. hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open-drain or three-state outputs. the 1-wire port of the ds24b33 is open drain with an internal circuit equivalent to that shown in figure 8. rx r pup i l v pup bus master open-drain port pin 100 mosfet tx rx tx data ds24b33 1-wire port rx = receive tx = transmit figure 8. hardware configuration
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles ______________________________________________________________________________________ 13 a multidrop bus consists of a 1-wire bus with multiple slaves attached. the ds24b33 supports both a stan- dard and overdrive communication speed of 15.4kbps (maximum) and 125kbps (maximum), respectively, over the full pullup voltage range. for pullup voltages of +4.75v and higher, the ds24b33 also supports the legacy communication speed of 16.3kbps and over- drive speed of 142kbps. the slightly reduced rates for the ds24b33 are a result of additional recovery times, which in turn were driven by a 1-wire physical interface enhancement to improve noise immunity. the value of the pullup resistor primarily depends on the network size and load conditions. the ds24b33 requires a pullup resistor of 2.2k (maximum) at any speed. the idle state for the 1-wire bus is high. if for any rea- son a transaction must be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16? (overdrive speed) or more than 120? (standard speed), one or more devices on the bus may be reset. transaction sequence the protocol for accessing the ds24b33 through the 1-wire port is as follows: initialization rom function commands memory function commands transaction/data initialization all transactions on the 1-wire bus begin with an initial- ization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds24b33 is on the bus and is ready to operate. for more details, see the 1-wire signaling section. 1-wire rom function commands once the bus master has detected a presence, it can issue one of the seven rom function commands that the ds24b33 supports. all rom function commands are 8 bits long. see figure 9 for a list of these commands. read rom [33h] this command allows the bus master to read the ds24b33? 8-bit family code, unique 48-bit serial num- ber, and 8-bit crc. this command can only be used if there is a single slave on the bus. if more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-and result). the resultant family code and 48-bit serial number results in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit rom sequence, allows the bus master to address a specific ds24b33 on a multidrop bus. only the ds24b33 that exactly matches the 64-bit rom sequence responds to the memory function command that follows. all other slaves wait for a reset pulse. this command can be used with a single device or multiple devices on the bus. search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1-wire bus or their registration numbers. by taking advantage of the bus? wired-and property, the master can use a process of elimination to identify the registration num- bers of all slave devices. for each bit of the registration number, starting with the lsb, the bus master issues a triplet of time slots. on the first slot, each slave device participating in the search outputs the true value of its registration number bit. on the second slot, each slave device participating in the search outputs the comple- mented value of its registration number bit. on the third slot, the master writes the true value of the bit to be selected. all slave devices that do not match the bit written by the master stop participating in the search. if both of the read bits are zero, the master knows that slave devices exist with both states of the bit. by choos- ing which state to write, the bus master branches in the rom code tree. after one complete pass, the bus mas- ter knows the registration number of a single device. additional passes identify the registration numbers of the remaining devices. refer to application note 187: 1-wire search algorithm for a detailed discussion and an example.
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles 14 ______________________________________________________________________________________ skip rom [cch] this command can save time in a single-drop bus sys- tem by allowing the bus master to access the memory functions without providing the 64-bit rom code. if more than one slave is present on the bus and, for example, a read command is issued following the skip rom command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-and result). resume [a5h] to maximize the data throughput in a multidrop envi- ronment, the resume command is available. this com- mand checks the status of the rc bit and, if it is set, directly transfers control to the memory functions, simi- lar to a skip rom command. the only way to set the rc bit is by successfully executing the match rom, search rom, or overdrive-match rom command. once the rc bit is set, the device can repeatedly be accessed through the resume command. accessing another device on the bus clears the rc bit, preventing two or more devices from simultaneously responding to the resume command. overdrive-skip rom [3ch] on a single-drop bus, this command can save time by allowing the bus master to access the memory func- tions without providing the 64-bit rom code. unlike the normal skip rom command, the overdrive-skip rom command sets the ds24b33 in the overdrive mode (od = 1). all communication following this command must occur at overdrive speed until a reset pulse of minimum 480? duration resets all devices on the bus to stan- dard speed (od = 0). when issued on a multidrop bus, this command sets all overdrive-supporting devices into overdrive mode. to subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed must be issued followed by a match rom or search rom com- mand sequence. this speeds up the time for the search process. if more than one slave supporting overdrive is present on the bus and the overdrive-skip rom command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired- and result). overdrive-match rom [69h] the overdrive-match rom command followed by a 64- bit rom sequence transmitted at overdrive speed allows the bus master to address a specific ds24b33 on a multidrop bus and to simultaneously set it in over- drive mode. only the ds24b33 that exactly matches the 64-bit rom sequence responds to the subsequent memory function command. slaves already in overdrive mode from a previous overdrive-skip rom or success- ful overdrive-match rom command remain in over- drive mode. all overdrive-capable slaves return to standard speed at the next reset pulse of minimum 480? duration. the overdrive-match rom command can be used with a single device or multiple devices on the bus.
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles ______________________________________________________________________________________ 15 ds24b33 tx presence pulse bus master tx reset pulse bus master tx rom function command ds24b33 tx crc byte ds24b33tx family code (1 byte) ds24b33 tx serial number (6 bytes) od = 0 rc = 0 master tx bit 0 rc = 0 rc = 0 od reset pulse? y y y y y y n 33h read rom command? n 55h match rom command? bit 0 match? bit 0 match? n n n n n n n f0h search rom command? nn y rc = 1 master tx bit 1 master tx bit 63 bit 1 match? bit 63 match? y y rc = 1 from memory functions flowchart (figure 7) to memory functions flowchart (figure 7) ds24b33 tx bit 0 ds24b33 tx bit 0 master tx bit 0 bit 1 match? bit 63 match? ds24b33 tx bit 1 ds24b33 tx bit 1 master tx bit 1 ds24b33 tx bit 63 ds24b33 tx bit 63 master tx bit 63 y from figure 9b to figure 9b to figure 9b from figure 9b rc = 0 y cch skip rom command? figure 9a. rom functions flowchart
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles 16 ______________________________________________________________________________________ master tx bit 0 rc = 0; od = 1 rc = 0; od = 1 od = 0 (see note) note: the od flag remains at 1 if the device was already at overdrive speed before the overdrive-match rom command was issued. (see note) (see note) rc = 1? y y a5h resume command? n y 3ch overdrive- skip rom? n y 69h overdrive- match rom? n n od = 0 n od = 0 n master tx bit 1 master tx bit 63 y y rc = 1 y bit 0 match? master tx reset? bit 63 match? bit 1 match? n y n y master tx reset? n to figure 9a from figure 9a from figure 9a to figure 9a figure 9b. rom functions flowchart (continued)
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles ______________________________________________________________________________________ 17 1-wire signaling the ds24b33 requires strict protocols to ensure data integrity. the protocol consists of four types of signaling on one line: reset sequence with reset pulse and pres- ence pulse, write-zero, write-one, and read-data. except for the presence pulse, the bus master initiates all falling edges. the ds24b33 can communicate at two different speeds: standard speed and overdrive speed. if not explicitly set into the overdrive mode, the ds24b33 communicates at standard speed. while in overdrive mode the fast timing applies to all waveforms. to get from idle to active, the voltage on the 1-wire line needs to fall from v pup below the threshold v tl . to get from active to idle, the voltage needs to rise from v ilmax past the threshold v th . the time it takes for the voltage to make this rise is seen in figure 10 as , and its duration depends on the pullup resistor (r pup ) used and the capacitance of the 1-wire network attached. the voltage v ilmax is relevant for the ds24b33 when determining a logical level, not triggering any events. figure 10 shows the initialization sequence required to begin any communication with the ds24b33. a reset pulse followed by a presence pulse indicates that the ds24b33 is ready to receive data, given the correct rom and memory function command. if the bus master uses slew-rate control on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge. a t rstl duration of 480? or longer exits the overdrive mode, returning the device to standard speed. if the ds24b33 is in overdrive mode and t rstl is no longer than 80?, the device remains in overdrive mode. if the device is in overdrive mode and t rstl is between 80? and 480?, the device resets, but the communication speed is undetermined. after the bus master has released the line it goes into receive mode. now the 1-wire bus is pulled to v pup through the pullup resistor, or in case of a ds2482-x00 or ds2480b driver, by active circuitry. when the thresh- old v th is crossed, the ds24b33 waits for t pdh and then transmits a presence pulse by pulling the line low for t pdl . to detect a presence pulse, the master must test the logical state of the 1-wire line at t msp . the t rsth window must be at least the sum of t pdhmax , t pdlmax , and t recmin . immediately after t rsth is expired, the ds24b33 is ready for data communication. in a mixed population network, t rsth should be extend- ed to minimum 480? at standard speed and 48? at overdrive speed to accommodate other 1-wire devices. read/write time slots data communication with the ds24b33 takes place in time slots, which carry a single bit each. write time slots transport data from bus master to slave. read time slots transfer data from slave to master. figure 11 illus- trates the definitions of the write and read time slots. all communication begins with the master pulling the data line low. as the voltage on the 1-wire line falls below the threshold v tl , the ds24b33 starts its internal timing generator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot. master-to-slave for a write-one time slot, the voltage on the data line must have crossed the v th threshold before the write- one low time t w1lmax is expired. for a write-zero time slot, the voltage on the data line must stay below the v th threshold until the write-zero low time t w0lmin is expired. for the most reliable communication, the resistor master ds24b33 t rstl t pdl t rsth t pdh master tx "reset pulse" master rx "presence pulse" v pup v ihmaster v th v tl v ilmax 0v t f t rec t msp figure 10. initialization procedure: reset and presence pulse
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles 18 ______________________________________________________________________________________ voltage on the data line should not exceed v ilmax dur- ing the entire t w0l or t w1l window. after the v th thresh- old has been crossed, the ds24b33 needs a recovery time t rec before it is ready for the next time slot. resistor master resistor master resistor master ds24b33 v pup v ihmaster v th v tl v ilmax 0v t f v pup v ihmaster v th v tl v ilmax 0v t f v pup v ihmaster v th v tl v ilmax 0v t f t slot t w1l t rec t slot t slot t w0l t rec master sampling window t rl t msr write-one time slot write-zero time slot read-data time slot figure 11. read/write timing diagrams
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles ______________________________________________________________________________________ 19 slave-to-master a read-data time slot begins like a write-one time slot. the voltage on the data line must remain below v tl until the read low time t rl is expired. during the t rl win- dow, when responding with a 0, the ds24b33 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. when responding with a 1, the ds24b33 does not hold the data line low at all, and the voltage starts rising as soon as t rl is over. the sum of t rl + (rise time) on one side and the inter- nal timing generator of the ds24b33 on the other side define the master sampling window (t msrmin to t msrmax ) in which the master must perform a read from the data line. for the most reliable communication, t rl should be as short as permissible, and the master should read close to but no later than t msrmax . after reading from the data line, the master must wait until t slot is expired. this guarantees sufficient recovery time t rec for the ds24b33 to get ready for the next time slot. note that t rec specified herein applies only to a single ds24b33 attached to a 1-wire line. for multide- vice configurations, t rec needs to be extended to accommodate the additional 1-wire device input capacitance. alternatively, an interface that performs active pullup during the 1-wire recovery time such as the ds2482-x00 or ds2480b 1-wire line drivers can be used. improved network behavior (switchpoint hysteresis) in a 1-wire environment, line termination is possible only during transients controlled by the bus master (1-wire driver). 1-wire networks, therefore, are suscep- tible to noise of various origins. depending on the phys- ical size and topology of the network, reflections from end points and branch points can add up or cancel each other to some extent. such reflections are visible as glitches or ringing on the 1-wire communication line. noise coupled onto the 1-wire line from external sources can also result in signal glitching. a glitch dur- ing the rising edge of a time slot can cause a slave device to lose synchronization with the master and, consequently, result in a search rom command com- ing to a dead end or cause a device-specific function command to abort. for better performance in network applications, the ds24b33 uses an improved 1-wire front-end, which makes it less sensitive to noise. the 1-wire front-end of the ds24b33 differs from tradi- tional slave devices in one characteristic: there is a hys- teresis at the low-to-high switching threshold v th . if a negative glitch crosses v th but does not go below v th - v hy , it is not recognized (figure 12). the hysteresis is effective at any 1-wire speed. crc generation the ds24b33 uses two different types of crcs. one crc is an 8-bit type and is stored in the most signifi- cant byte of the 64-bit registration number. the bus master can compute a crc value from the first 56 bits of the 64-bit registration number and compare it to the value stored within the ds24b33 to determine if the reg- istration number has been received error-free. the equivalent polynomial function of this crc is x 8 + x 5 + x 4 + 1. this 8-bit crc is received in the true (noninvert- ed) form. it is computed and programmed into the chip at the factory. the other crc is a 16-bit type, generated according to the standardized crc-16 polynomial function x 16 + x 15 + x 2 + 1. this crc is used for fast verification of a data transfer when writing to the scratchpad. in contrast to the 8-bit crc, the 16-bit crc is always communicated in the inverted form. a crc generator inside the ds24b33 (figure 13) calculates a new 16-bit crc, as shown in the command flowchart (figure 7). the bus master compares the crc value read from the device to the one it calculates from the data, and decides whether to continue with an operation. with the write scratchpad command, the crc is gen- erated by first clearing the crc generator and then shifting in the command code, the target addresses ta1 and ta2, and all the data bytes as they were sent by the bus master. the ds24b33 transmits this crc only if the data bytes written to the scratchpad include scratchpad ending offset 11111b. the data can start at any location within the scratchpad. for more information on generating crc values refer to application note 27: understanding and using cyclic redundancy checks with maxim i button products . v pup v th v hy 0v figure 12. hysteresis at the low-to-high switching threshold
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles 20 ______________________________________________________________________________________ 1st stage 2nd stage 3rd stage 4th stage 7th stage 8th stage 6th stage 5th stage x 0 x 1 x 2 x 3 x 4 polynomial = x 16 + x 15 + x 2 + 1 input data crc output x 5 x 6 11th stage 12th stage 15th stage 14th stage 13th stage x 11 x 12 9th stage 10th stage x 9 x 10 x 13 x 14 x 7 16th stage x 16 x 15 x 8 figure 13. crc-16 hardware description and polynomial symbol description rst 1-wire reset pulse generated by master pd 1-wire presence pulse generated by slave select command and data to satisfy the rom function protocol ws command: write scratchpad rs command: read scratchpad cps command: copy scratchpad rm command: read memory ta target address ta1, ta2 ta-e/s target address ta1, ta2 with e/s byte transfer of as many bytes as needed to reach the end of the scratchpad for a given target address transfer of as many bytes as are needed to reach the end of the memory crc-16 transfer of an inverted crc-16 ff loop indefinite loop where the master reads ff bytes aa loop indefinite loop where the master reads aa bytes programming data transfer to eeprom; no activity on the 1-wire bus permitted during this time command-specific 1-wire communication protocol?egend
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles ______________________________________________________________________________________ 21 master-to-slave slave-to-master programming command-specific 1-wire communication protocol?olor codes rst ws write scratchpad, reaching the end of the scratchpad pd ta select ff loop crc-16 read scratchpad copy scratchpad (success) copy scratchpad (fail ta-e/s) rst rs pd ta-e/s select ff loop rst cps pd ta-e/s select ff loop rst rm ta pd select ff loop rst cps pd ta-e/s select aa loop read memory programming 1-wire communication examples package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per tains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 so w8+2 21-0262 90-0258 3 to-92 (bulk) q3+1 21-0248 3 to-92 (t&r) q3+1 21-0250
ds24b33 4kb 1-wire eeprom with 200k write/erase cycles maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 2/11 initial release

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